In processor-based platforms, lower platform power and maximized battery life are desirable features. Low hardware power states and memory self refresh modes, among others, may be used to reduce power consumption and increase battery life. It is desirable on power managed platforms to move as much of the hardware into low power states as possible, when feasible, and to increase memory self refresh time in order to minimize total platform power.
Some platforms may include components or functionality based on specialized hardware, often termed hardware acceleration. An example is a video decode data flow, which may pass data through multiple stages such as for example, a decoding stage, an image enhancement stage, and a composition stage as is known in the art. Several approaches can be used in order to lower the power consumption. One approach is to run a multi-stage hardware acceleration process such as a video decoder by pipeline processing through the stages so that all the stages are run in parallel, and then are shut down or idled until the next frame is scheduled to be processed. This approach may be based on an assumption that a parallelized pipeline leaves the platform most of the time in an idle mode, which enables a low power state for the various components.